As the drive for the continued miniaturization proceeds apace, various issues arise imposing increasing demands for methodology enabling the fabrication of semiconductor devices having accurately dimensioned microminiaturized features. As the gate width for transistors decreases to about 400 Å and under, various dimensional accuracy issues arise.
Semiconductor device features, such as a gate width are typically patterned employing an overlying structure comprising a layer functioning as an anti-reflective coating (ARC) during photoresist patterning and a layer functioning as a hardmask during patterning of an underlying patternable layer. For example, adverting to FIG. 1A, an intermediate structure employed to form a gate electrode is illustrated and comprises a semiconductor substrate 10, isolation regions 12 defining an active area, a conformal gate insulating layer 14, such as silicon oxide, and a patternable gate conductive layer 16, such as polysilicon, formed over the gate insulating layer 14. A bi-layer ARC/hardmask structure is formed over the gate conductive layer 16 and comprises ARC 20, such as silicon oxynitride typically deposited by plasma enhanced chemical vapor deposition (PECVD) and hardmask 18, such as amorphous carbon which may be doped with nitrogen to improve its etch selectively with respect to the underlying polysilicon 16. A photomask 12 is formed on the silicon oxynitride layer 20 and is used to pattern the silicon oxynitride layer 20 which, in turn, is employed as a hardmask to pattern amorphous carbon layer 18 which, in turn, is used as a hardmask to pattern polysilicon layer 16 to form a gate electrode.
As critical dimensions of semiconductor devices shrink, such as the gate width, it is necessary to decrease the thickness of the overlying ARC/hardmask structure, such as the bi-layer silicon oxynitride ARC 20/amorphous carbon hardmask layer 18 illustrated in FIG. 1A. However, as the gate width is reduced to 400 A and less, the required reduction in thickness of the overlying ARC/hardmask generates various problems. For example, as the silicon oxynitride ARC is decreased in thickness, “pinholes” occur. Such pinholes are believed to be generated by outgassing from underlying layers during deposition of the PECVD material. For example, when silicon oxynitride is deposited by PECVD over an amorphous carbon layer, residual hydrogen from the amorphous carbon layer is emitted, thereby causing localized non-uniformities in the PECVD silicon oxynitride layer. During PECVD deposition of silicon oxynitride, reduced deposition occurs proximate the non-uniformities, thereby generating pinholes that extend partly or entirely through the silicon oxynitride layer from locations of the non-uniformities.
The occurrence of pinholes result in at least two serious problems. One problem generated by pinholes is photoresist poisoning. Adverting to FIG. 1B, pinhole 24 enables diffusion of nitrogen doping from the amorphous carbon layer 18 into an overlying photoresist layer 26 forming a region of poisoned photoresist 28. Poisoned photoresist exhibits reduced response to conventional photoresist development chemistries and, consequently, remain after development causing undesired patterning of underlying layers during subsequent processing.
Another problem stemming from pinholes is premature etching of the amorphous carbon layer during reworking of the photoresist. During typical processing, photoresist layers are applied over the bi-layer ARC/hardmask, patterned and removed several times. Adverting to FIG. 1C during removal of the photoresist, the chemistry used to strip the photoresist may pass through a pinhole and contact the underlying amorphous carbon layer, causing etching as in region 30 in the amorphous carbon layer 18. This results in the formation of anomalous patterns in the amorphous carbon layer that may be transferred to underlying layers during subsequent processing. Such etching has been found to occur even with pinholes that did not extend completely through the silicon oxynitride layer 26, a phenomenon known as “punch through.”
Accordingly, there exists a need for methodology enabling fabrication of semiconductor devices having accurately patterned microminiaturized features. There exists a particular need for methodology enabling fabrication of accurately dimensioned gate electrodes having a width of 400 Å or less.